The invention relates to the formation of integrated circuits in general, and more particularly, to the formation of active areas in integrated circuits.
Some conventional methods of forming trench isolation regions include forming a trench region in a substrate and filling the trench with a dielectric layer. In some of these conventional methods, the trench isolation region is formed relatively deep and narrow to increase the density of the integrated circuits in which the trench isolation structure is formed. Trench isolation regions formed using these types of conventional methods can provide good results.
However, some conventionally formed trench isolation regions, such as those described above, can develop an electric field that is concentrated at a border between the trench isolation region and an active region adjacent thereto. In particular, the electric field can develop at an upper side wall of the trench isolation region which can lead to the development of a channel inversion layer at the upper side wall of the trench isolation region (or at the edge of the active region) adjacent to the channel region of a transistor. The channel inversion layer can cause a leakage current at the upper side wall of the trench isolation region between a source region and a drain region of the transistor when a voltage applied to the gate electrode is less than a threshold voltage of the transistor. This phenomenon is sometimes referred to as an inverse narrow width effect and is further discussed in xe2x80x9cSilicon Processing for the VLSI ERA Volume 3xe2x80x9d by Stanley Wolf, Lattice Process, pp. 222-226., and in U.S. Pat. No. 5,960,276 to Liaw et al. and U.S. Pat. No. 5,057,444 to Fuse et al. U.S. Pat. No. 6,245624 to Kim et al. discusses lightly doped drain regions in integrated circuits.
Active areas of integrated circuits can be formed according to embodiments of the invention by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a leakage current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited.
In transistor devices according to the invention, an isolation structure is located in an integrated circuit substrate. An active region of the substrate is adjacent to the isolation structure, the active area includes a source region of the transistor and a drain region of the transistor having a channel region therebetween. A first active area of the active region is adjacent to the isolation structure and has a first concentration level of ions of a conductivity type. A second active area is in the active region and is separated from the isolation structure by the first active area and has a second concentration level of ions of the conductivity type that is less than the first concentration level of ions.